Quantum Dot Cellular Automata
The seemingly endless progress of microelectronics has been a result of the semiconductor industry’s ability to continuously scale down the transistor, which is the fundamental computing component of the modern computer. Scaling of the transistor to low-nanometer scales is limited by effects such as gate leakage, drain induced barrier lowering, and the extreme power dissipation. Molecular quantum cellular automata (QCA) is an exploratory computing paradigm in which information is encoded in the electronic charge configuration of a QCA cell. The charge interaction between neighbouring cells enables the transmission and processing of information. The underlying building block of any QCA circuit is the QCA cell, which is constructed with either a single molecule or a set of coupled quantum dots (in quantum-dot cellular automata (QCA)) or metallic islands (in metallic-island QCA). Members of our lab have developed a QCA design and simulation tool called QCADesigner. This tool is being used to evaluate this emerging technology by looking a circuits and computer architectures that can be implemented with QCA.
QCADesigner is the product of an ongoing research effort by the Walus Lab at the University of British Columbia (UBC) to create a design and simulation tool for Quantum Dot Cellular Automata (QCA). This tool is still under development and is provided free of cost to the research community “as is”. QCA is an emerging concept in computational nanotechnology for the realization of a computer using arrays of nano-scale QCA cells. These QCA cells are capable of performing all complex computational functions required for general-purpose computation (majority function, Inversion, and fan-out). The QCADesigner tool facilitates rapid design, layout and simulation of QCA circuits by providing powerful CAD features available in more complex circuit design tools.
Faizal Calendar (FiCal)
FiCal is a time-management web application. The interface of FiCal is similar to Google Calendar and iCal and enables users to view, add, and change events from one date to another without reloading the page. It currently only supports monthly view modes, but future updates will allow weekly, agenda and custom view modes as well. Events are added into the calendar by clicking on the date of interest, and editing the "Events list". Events on the list are added into a mySQL database and thus can be viewed and edited from any location that has internet access.
In the next update, FiCal will allow multiple calendars to be created and shown in the same view. Each calendar will have the ability to be shared, either read-only or full edit control, and either with specified users or with everyone.
The availability of nano fabrication processes and the demand for smaller, more power efficient technology has led to the research and development of a wide-range of novel computing paradigms at the nanoscale. Many of these emergent technologies such as quantum-dot cellular automata (QCA), resonant tunneling diodes (RTD), single electron tunneling (SET), and tunnel phase logic (TPL) are capable of implementing majority and minority logic. As a result of this, it is important to be able to effectively model and test for the various faults in these majority/minority based logic circuits - particularly in light of the fact that these nano circuits are difficult to realize without defects.
Amongst the numerous potential faults likely to occur in such circuits, single stuck-at faults (SSF) and single bridging faults (SBF) represent a large portion of the general faults that occur in these systems. In the SSF model, a line in a circuit is assumed to be permanently stuck-at-1 (SA1) or stuck-at-0 (SA0). The SBF model is commonly used when a pair of interconnects is assumed to be shorted. Several algorithms have already been proposed to automatically generate test patterns for SSFs and SBFs in CMOS circuits. However, it remains to be seen whether or not the conventional CMOS test flow can accommodate the testing of nanotechnologies.
To this effect, I developed an extension to the existing Path Oriented DEcision Making (PODEM) algorithm to include the ability to generate test patterns for single stuck- at and bridging faults in majority and minority networks. This algorithm is directly applicable to QCA, RTD, SET, and TPL. A dynamic probability-based controllability heuristic was developed and used as a guide to make intelligent decisions on which lines to justify during the automatic test pattern generation (ATPG) process. Lastly, a genetic algorithm is used to fill-in the unspecified values in the test patterns produced by the ATPG in order to achieve compaction on the final test set size. The modified PODEM algorithm was tested on a set of Microelectronics Center of North Carolina (MCNC) benchmark circuits. In most cases, the size of the resulting test sets using this method was less than 5% of the total number of possible input patterns. This represents a significant upgrade on the existing tools used to test these emergent nanotechnologies.